[all-commits] [llvm/llvm-project] b0c2f9: [RISCV] Merge more rv32/rv64 vector intrinsic test...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0c2f9045394211c489c9e7777deef682e6701ba
      https://github.com/llvm/llvm-project/commit/b0c2f9045394211c489c9e7777deef682e6701ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-10-08 (Sat, 08 Oct 2022)

  Changed paths:
    R llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vadc.ll
    R llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vand.ll
    R llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vdiv.ll
    R llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vdivu.ll
    R llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vleff.ll
    R llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmacc.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadc.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmadd.ll
    R llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmax.ll
    R llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmaxu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmin.ll
    R llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vminu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
    R llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmseq.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsge.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsle.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmslt.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vmsne.ll
    R llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vnmsac.ll
    R llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vnmsub.ll
    R llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vor.ll
    R llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vrem.ll
    R llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vremu.ll
    R llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vsbc.ll
    R llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
    R llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vselect-int.ll
    R llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    R llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vxor.ll

  Log Message:
  -----------
  [RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.