[all-commits] [llvm/llvm-project] 027516: [RISCV] Verify that policy operands only exist on ...
Philip Reames via All-commits
all-commits at lists.llvm.org
Thu Oct 6 15:19:14 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 027516553da4d380a9a7ea673342dba61318cc47
https://github.com/llvm/llvm-project/commit/027516553da4d380a9a7ea673342dba61318cc47
Author: Philip Reames <preames at rivosinc.com>
Date: 2022-10-06 (Thu, 06 Oct 2022)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV] Verify that policy operands only exist on instructions with tied passthru operands
This is a non-trivial property relied upon by D135396. I wrote this to convince myself it was true.
Differential Revision: https://reviews.llvm.org/D135403
Commit: 79f0413e5e3cc775d0c116b66e3ff7fb82f1ee54
https://github.com/llvm/llvm-project/commit/79f0413e5e3cc775d0c116b66e3ff7fb82f1ee54
Author: Philip Reames <preames at rivosinc.com>
Date: 2022-10-06 (Thu, 06 Oct 2022)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/uadd_sat.ll
M llvm/test/CodeGen/RISCV/uadd_sat_plus.ll
Log Message:
-----------
[RISCV] Use branchless form for selects with -1 in either arm
We can lower these as an or with the negative of the condition value. This appears to result in significantly less branch-y code on multiple common idioms (as seen in tests).
Differential Revision: https://reviews.llvm.org/D135316
Compare: https://github.com/llvm/llvm-project/compare/76ac3b89173e...79f0413e5e3c
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