[all-commits] [llvm/llvm-project] d89d45: [RISCV][InsertVSETVLI] Default to MA not MU

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d89d45ca9a6e51be388a6ff3893d59e54748b928
      https://github.com/llvm/llvm-project/commit/d89d45ca9a6e51be388a6ff3893d59e54748b928
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-10-06 (Thu, 06 Oct 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/fold-vector-cmp.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
    M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-fpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast-large-vector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vw-web-simplification.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
    M llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
    M llvm/test/CodeGen/RISCV/rvv/load-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/marith-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
    M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-combine.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/pr52475.ll
    M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/select-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/select-int.ll
    M llvm/test/CodeGen/RISCV/rvv/select-sra.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/smulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/splats-with-mixed-vl.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress.ll
    M llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vcpop.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfirst.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vid.ll
    M llvm/test/CodeGen/RISCV/rvv/viota.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vle.ll
    M llvm/test/CodeGen/RISCV/rvv/vle_vid-vfcvt.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlm.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmand.ll
    M llvm/test/CodeGen/RISCV/rvv/vmandn.ll
    M llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmclr.ll
    M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmnand.ll
    M llvm/test/CodeGen/RISCV/rvv/vmnor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmorn.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmset.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmxnor.ll
    M llvm/test/CodeGen/RISCV/rvv/vmxor.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vse.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-constant-vl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-constant-vl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext.ll
    M llvm/test/CodeGen/RISCV/rvv/wrong-chain-fixed-load.ll
    M llvm/test/CodeGen/RISCV/rvv/zve32-types.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
    M llvm/test/CodeGen/RISCV/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/vadd-vp-mask.ll
    M llvm/test/CodeGen/RISCV/vmul-vp-mask.ll
    M llvm/test/CodeGen/RISCV/vsub-vp-mask.ll

  Log Message:
  -----------
  [RISCV][InsertVSETVLI] Default to MA not MU

This changes the default value used for mask policy from mask undisturbed to mask agnostic. In hardware, there may be a minor preference for ta/ma, but since this is only going to apply to instructions which don't use the mask policy bit, this is functionally mostly a nop. The main value is to make future changes to using MA when legal for masked instructions easier to review by reducing test churn.

The prior code was motivated by a desire to minimize state transitions between masked and unmasked code. This patch achieves the same effect using the demanded field logic (landed in afb45ff), and there are no regressions I spotted in the test diffs. (Given the size, I have only been able to skim.) I do want to call out that regressions are possible here; the demanded analysis only works on a block local scope right now, so e.g. a tight loop mixing masked and unmasked computation might see an extra vsetvli or two.

Differential Revision: https://reviews.llvm.org/D133803