[all-commits] [llvm/llvm-project] 203d0b: [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.

[Joe Nash via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 203d0b0ee1369b1479da98922797ce68827fcd55
      https://github.com/llvm/llvm-project/commit/203d0b0ee1369b1479da98922797ce68827fcd55
  Author: Joe Nash <Joseph.Nash at amd.com>
  Date:   2022-10-05 (Wed, 05 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/VOPCInstructions.td
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3c.s
    M llvm/test/MC/AMDGPU/gfx11_asm_vop3cx.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3c.txt
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3cx.txt

  Log Message:
  -----------
  [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type.

For V_CMP_CLASS_F16_t16_e64 and V_CMPX_CLASS_F16_t16_e64,
https://reviews.llvm.org/D133723 changed the value type of src1 from i32 to i16.
These src1 operands are 16 bits, therefore need to be encoded as true16
operands. So the _e32 type was correctly set to VGPR_32_Lo128.
In _e64 form the operand class went from
VSrc_b32 to VSrc_b16. For some reason, we cannot encode inline literals for
VSrc_b16, see 5f5f566b265db00f577ead268400d99f34ba9cdd. In this phase of
the true16 implementation, VSrc_b16 and VSrc_b32 are still similar,
except from that quirk of inlines. So set the operand class to regain
that function.

Reviewed By: dp, arsenm

Differential Revision: https://reviews.llvm.org/D134897