[all-commits] [llvm/llvm-project] cebec4: [DAGCombiner] [AMDGPU] Allow vector loads in Match...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cebec4208982dccb70e724e38fca72823652ec76
      https://github.com/llvm/llvm-project/commit/cebec4208982dccb70e724e38fca72823652ec76
  Author: jeff <Jeffrey.Byrnes at amd.com>
  Date:   2022-10-04 (Tue, 04 Oct 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/load-combine.ll
    M llvm/test/CodeGen/AMDGPU/combine-vload-extract.ll
    M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
    M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll

  Log Message:
  -----------
  [DAGCombiner] [AMDGPU] Allow vector loads in MatchLoadCombine

Since SROA chooses promotion based on reaching load / stores of allocas, we may run into scenarios in which we alloca a vector, but promote it to an integer. The result of which is the familiar LoadCombine pattern (i.e. ZEXT, SHL, OR). However, instead of coming directly from distinct loads, the elements to be combined are coming from ExtractVectorElements which stem from a shared load.

This patch identifies such a pattern and combines it into a load.

Change-Id: I0bc06588f11e88a0a975cde1fd71e9143e6c42dd