[all-commits] [llvm/llvm-project] 4ea121: [PowerPC] Fix a number of inefficiencies and issue...

Nemanja Ivanovic via All-commits all-commits at lists.llvm.org
Mon Oct 3 17:58:12 PDT 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4ea121c904b9c9cffd49d0b92d5b6680e310d757
      https://github.com/llvm/llvm-project/commit/4ea121c904b9c9cffd49d0b92d5b6680e310d757
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2022-10-03 (Mon, 03 Oct 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsPowerPC.td
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    M llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
    M llvm/test/CodeGen/PowerPC/all-atomics.ll
    M llvm/test/CodeGen/PowerPC/atomic-1.ll
    M llvm/test/CodeGen/PowerPC/atomic-2.ll
    M llvm/test/CodeGen/PowerPC/atomic-float.ll
    M llvm/test/CodeGen/PowerPC/atomic-minmax.ll
    M llvm/test/CodeGen/PowerPC/atomics-regression.ll
    M llvm/test/CodeGen/PowerPC/atomics.ll
    A llvm/test/CodeGen/PowerPC/branch-on-store-cond.ll
    M llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
    M llvm/test/CodeGen/PowerPC/loop-comment.ll
    M llvm/test/CodeGen/PowerPC/pr30451.ll
    M llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll

  Log Message:
  -----------
  [PowerPC] Fix a number of inefficiencies and issues with atomic code gen

There are a few issues with the code we generate for atomic operations and the way we generate it:

- Hard coded CR0 for compares
- Order of operands for compares not conducive to
  emitting compare-immediate or for CSE of compares
- Missing MachineMemOperand for st[bhwd]cx intrinsics
- Missing intrinsic properties for the same
- Unnecessary blocks with store conditional
  instructions to clear reservation (which ends
  up hindering performance)
- Move from CR instructions just to compare the
  result of a store conditional with zero (even
  though it is a record-form)

This patch aims to resolve all of those issues.

Differential revision: https://reviews.llvm.org/D134783




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