[all-commits] [llvm/llvm-project] 07ccf6: x[AArch64][GlobalISel] Enable vector support for G...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 07ccf651b95b3d92904e5d513772ad51567d8334
      https://github.com/llvm/llvm-project/commit/07ccf651b95b3d92904e5d513772ad51567d8334
  Author: Amara Emerson <amara at apple.com>
  Date:   2022-10-03 (Mon, 03 Oct 2022)

  Changed paths:
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaximum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminimum.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
    A llvm/test/CodeGen/AArch64/GlobalISel/select-to-fmin-fmax.ll

  Log Message:
  -----------
  x[AArch64][GlobalISel] Enable vector support for G_SELECT->G_FMAXIMUM/MINIMUM.

Vector support seems to work immediately, as long as we run the combine before
legalization (so the vector SELECTs don't get lowered) and the legalizer rules
are there to enable generation.

Differential Revision: https://reviews.llvm.org/D135047


  Commit: dcd02a524befcec71f46ab76d725b2a8f8623d69
      https://github.com/llvm/llvm-project/commit/dcd02a524befcec71f46ab76d725b2a8f8623d69
  Author: Amara Emerson <amara at apple.com>
  Date:   2022-10-03 (Mon, 03 Oct 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    A llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sext-of-vcmp.mir
    M llvm/test/CodeGen/AArch64/arm64-vabs.ll
    M llvm/test/CodeGen/AArch64/min-max.ll
    M llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares.

This fixes a long standing cause of awful code generation when legalization creates
G_SEXT(G_FCMP(...)), for example due to promoting the condition of a vector G_SELECT.

Since on AArch64 vector compares sign-extend the condition value, there's no need
for this extra G_SEXT. Unfortunately by the time we get to post-legalization these
G_SEXTs have already been lowered into shifts, so this combine is a bit more
involved than I'd ideally like. Oh well.

Differential Revision: https://reviews.llvm.org/D135078


Compare: https://github.com/llvm/llvm-project/compare/54608b40eb50...dcd02a524bef