[all-commits] [llvm/llvm-project] 938f41: [mlir][sparse] Avoid generating DimOp in conversio...

[PeimingLiu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 938f419cf1910b79388896c9694e58efc5325cba
      https://github.com/llvm/llvm-project/commit/938f419cf1910b79388896c9694e58efc5325cba
  Author: Peiming Liu <peiming at google.com>
  Date:   2022-09-09 (Fri, 09 Sep 2022)

  Changed paths:
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp

  Log Message:
  -----------
  [mlir][sparse] Avoid generating DimOp in conversion passes.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D133592