[all-commits] [llvm/llvm-project] edb262: [VPlan] Only generate single instr for stores unif...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: edb26268ce6e915377086fa1a3733254f64aeda3
      https://github.com/llvm/llvm-project/commit/edb26268ce6e915377086fa1a3733254f64aeda3
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-09-09 (Fri, 09 Sep 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll

  Log Message:
  -----------
  [VPlan] Only generate single instr for stores uniform across all parts.

Extend the approach taken by D133019 to store instructions.

Differential Revision: https://reviews.llvm.org/D133497