[all-commits] [llvm/llvm-project] e26cad: [ARM] Constant pools need 4-byte alignment if we o...

[john-brawn-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e26cadcc32a2194610963bfe140795e978349ba2
      https://github.com/llvm/llvm-project/commit/e26cadcc32a2194610963bfe140795e978349ba2
  Author: John Brawn <john.brawn at arm.com>
  Date:   2022-09-06 (Tue, 06 Sep 2022)

  Changed paths:
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/test/CodeGen/ARM/cttz.ll

  Log Message:
  -----------
  [ARM] Constant pools need 4-byte alignment if we only have tADR

When the only ADR instruction we have is the 16-bit thumb one then all
constant pool entries need to be 4-byte aligned, as tADR has an offset
that's a multiple of 4.

It looks like previously there happened to be no situations in which
we encountered a constant pool entry with alignment less than 4, so
failing to do this didn't cause any problems, but the expansion of
cttz to a table added by D128911 does use a constant pool with
alignment 1, so we now need to handle it correctly.

Differential Revision: https://reviews.llvm.org/D133199