[all-commits] [llvm/llvm-project] c45810: [RISCV] When ISD::SETUGT && Imm == -1, has process...

[LiqinWeng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c45810f81079bf35818baef248ebf37428d228b7
      https://github.com/llvm/llvm-project/commit/c45810f81079bf35818baef248ebf37428d228b7
  Author: liqinweng <Liqin.Weng at streamcomputing.com>
  Date:   2022-09-01 (Thu, 01 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] When ISD::SETUGT && Imm == -1, has processed before lowering

When ISD::SETUGT && Imm == -1, has processed before lowering. Use assert replace it

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132373