[all-commits] [llvm/llvm-project] 893f5e: [RISCV] Improve isel of AND with shiftedMask conta...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 893f5e95e254e000222513b5fea1921f1796145c
      https://github.com/llvm/llvm-project/commit/893f5e95e254e000222513b5fea1921f1796145c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-30 (Tue, 30 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/and.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rv64zba.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/vararg.ll

  Log Message:
  -----------
  [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and some trailing zeros.

We can use srliw to shift out the trailing bits and slli to shift
back in zeros. The sign extend of srliw will 0 the upper 32 bits
since we will be shifting a 0 into bit 31.