[all-commits] [llvm/llvm-project] 050dad: [AArch64][GISel] constrain regclass for 128->64 copy
tmatheson-arm via All-commits
all-commits at lists.llvm.org
Tue Aug 30 03:03:19 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 050dad57f7e1a00933cb5bf31ffd671680c03ee3
https://github.com/llvm/llvm-project/commit/050dad57f7e1a00933cb5bf31ffd671680c03ee3
Author: Tomas Matheson <tomas.matheson at arm.com>
Date: 2022-08-30 (Tue, 30 Aug 2022)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
Log Message:
-----------
[AArch64][GISel] constrain regclass for 128->64 copy
When selecting G_EXTRACT to COPY for extracting a 64-bit GPR from
a 128-bit register pair (XSeqPair) we know enough to constrain the
destination register class to gpr64. Without this it may have only
a register bank and some copy elimination code would assert while
assuming that a register class existed.
The register class has to be set explicitly because we might hit the
COPY -> COPY case where register class can't be inferred.
This would cause the following to crash in selection, where the store
is commented (otherwise the store constrains the register class):
define dso_local i128 @load_atomic_i128_unordered(i128* %p) {
%pair = cmpxchg i128* %p, i128 0, i128 0 acquire acquire
%val = extractvalue { i128, i1 } %pair, 0
; store i128 %val, i128* %p
ret i128 %val
}
Differential Revision: https://reviews.llvm.org/D132665
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