[all-commits] [llvm/llvm-project] 5bd92d: [RISCV] Add test for failure to use ANDI and SRLIW...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5bd92d21b07e69c63f1bf91a0e7c350cc0a1ca92
      https://github.com/llvm/llvm-project/commit/5bd92d21b07e69c63f1bf91a0e7c350cc0a1ca92
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Add test for failure to use ANDI and SRLIW due to SimplifyDemandedBits.


  Commit: e25eb61d031bc01940aca1481adc05ad28f72628
      https://github.com/llvm/llvm-project/commit/e25eb61d031bc01940aca1481adc05ad28f72628
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Enable (srl (and X, C2), C) to form SRLIW in more cases.

Don't require the AND has one use and don't depend on
targetShrinkDemandedConstant turning C2 into 0xffffffff. Instead,
check that the constant is 0xffffffff after replacing any bits
that will be shifted out with 1s.

Another way to fix this might be to prevent SimplifyDemandedBits
from destroying the ANDI after type legalization using
targetShrinkDemandedBits. That would prevent the CSE that created
this mess. targetShrinkDemandedBits is currently only enable after
legalize ops. Quick experiment shows we can't just change when it
runs, we would need to try a different heuristic for post type
legalization.


Compare: https://github.com/llvm/llvm-project/compare/5b569ed2cdfb...e25eb61d031b