[all-commits] [llvm/llvm-project] 7c17b0: [RISCV] Add test case for missed opportunity to us...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c17b0afb10590b7c0fd2e63f9a82e1c49c3fec3
      https://github.com/llvm/llvm-project/commit/7c17b0afb10590b7c0fd2e63f9a82e1c49c3fec3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Add test case for missed opportunity to use ANDI.

Immediate was messed up by SimplfyDemandedBits.


  Commit: 0fbe71e91f44034bdd3f0df4183951f8af1ef958
      https://github.com/llvm/llvm-project/commit/0fbe71e91f44034bdd3f0df4183951f8af1ef958
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Use hasAllWUsers to recover ANDI.

SimplifyDemandedBits can 0 the upper bits and targetShrinkDemandedConstant
isn't alway able to recover it.

At least part of that may be because targetShrinkDemandedConstant
only runs in the last DAGCombine. Might be worth seeing what happens
if we move it post type legalization.


Compare: https://github.com/llvm/llvm-project/compare/329b972d416a...0fbe71e91f44