[all-commits] [llvm/llvm-project] 9d12bb: [RISCV] Apply DeMorgan to (beqz (and/or (seteq), (...

Craig Topper via All-commits all-commits at lists.llvm.org
Mon Aug 29 12:28:32 PDT 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d12bb77f912ec2257e334fe47ad6af52243d58a
      https://github.com/llvm/llvm-project/commit/9d12bb77f912ec2257e334fe47ad6af52243d58a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/setcc-logic.ll

  Log Message:
  -----------
  [RISCV] Apply DeMorgan to (beqz (and/or (seteq), (xor Z, 1))) to remove the xor.

We can rewrite to (bnez (or/and (setne), Z) is Z is 0/1.

Alternatively, we could canonicalize to (xor (or/and (setne), Z), 1)
even if there is no branch. The xor would not always get removed,
but it might enable other DeMorgan combines. I decided to be
conservative for this first patch and require the xor to be removed.

I have a couple other invertible setccs I will add in a follow up
patch.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132771


  Commit: 34e83525aac94ca00b8a3eb732910c3a7065da59
      https://github.com/llvm/llvm-project/commit/34e83525aac94ca00b8a3eb732910c3a7065da59
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/setcc-logic.ll

  Log Message:
  -----------
  [RISCV] Pre-commit tests for D132798. NFC


  Commit: 1c334b306e08a186c44fed8cb5d46076d569acf4
      https://github.com/llvm/llvm-project/commit/1c334b306e08a186c44fed8cb5d46076d569acf4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-29 (Mon, 29 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/setcc-logic.ll

  Log Message:
  -----------
  [RISCV] Add more invertible setccs to tryDemorganOfBooleanCondition.

This builds on D132771 to invert (setlt 0, X) to (setlt X, 1) and
vice versa.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132798


Compare: https://github.com/llvm/llvm-project/compare/288576f474f2...1c334b306e08


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