[all-commits] [llvm/llvm-project] 7167a4: [RISCV] Add zihintntl instructions

[Shao-Ce SUN via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7167a4207ee2c07cb192da1788f919332f83b456
      https://github.com/llvm/llvm-project/commit/7167a4207ee2c07cb192da1788f919332f83b456
  Author: Shao-Ce SUN <sunshaoce at iscas.ac.cn>
  Date:   2022-08-22 (Mon, 22 Aug 2022)

  Changed paths:
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/attributes.ll
    A llvm/test/MC/RISCV/rv32zihintntl-valid.s

  Log Message:
  -----------
  [RISCV] Add zihintntl instructions

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D121670