[all-commits] [llvm/llvm-project] 3e6d1a: [NFC][AArch64] Precommit test to optimize instruct...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3e6d1a6f54264bb50216069c68845b57428fc932
      https://github.com/llvm/llvm-project/commit/3e6d1a6f54264bb50216069c68845b57428fc932
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    A llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
    M llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

  Log Message:
  -----------
  [NFC][AArch64] Precommit test to optimize instruction selection for aarch64_neon_pmull64 intrinsic.

Differential Revision: https://reviews.llvm.org/D131045


  Commit: 945a3065015a62cf3b4ceabaa0755500fc7ddd71
      https://github.com/llvm/llvm-project/commit/945a3065015a62cf3b4ceabaa0755500fc7ddd71
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
    M llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

  Log Message:
  -----------
  [AArch64] Change aarch64_neon_pmull{,64} intrinsic ISel through a new
SDNode.

How:
1) Add AArch64ISD::PMULL SDNode, and extend aarch64_neon_pmull intrinsic
   tablegen pattern for this SDNode.
2) For aarch64_neon_pmull64, canonicalize i64 operands to v1i64 vectors
   during legalization.
3) For {aarch64_neon_pmull, aarch64_neon_pmull64}, combine intrinsic to
   SDNode.

Why
1) Adding the SDNode makes it easier to canonicalize i64 inputs (required by
   aarch64_neon_pmull64) to vector inputs. Vector inputs carries lane
   information, which helps dag-combiner to combine nodes (e.g. rewrite to a
   better node to prepare for instruction selection) and instruction-selection
   to emit instructions that use higher-half inputs in place
   (i.e., no need to move lane 1 content to lane 0).
2) Using the SDNode for aarch64_neon_pmull64 is NFC, yet without this we
   have to move the definition of {PMULLv1i64, PMULLv2i64} out of its
   current group of records without gains.

Test cases are commented with what is being tested in
`aarch64-pmull2.ll` and `pmull-ldr-merge.ll` under directory
`llvm/test/CodeGen/AArch64`.

Differential Revision: https://reviews.llvm.org/D131047


Compare: https://github.com/llvm/llvm-project/compare/4d977663167e...945a3065015a