[all-commits] [llvm/llvm-project] 3a7290: [IR] Update llvm.prefetch to match docs

Sam Elliott via All-commits all-commits at lists.llvm.org
Fri Aug 19 01:12:17 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a729069e463440035284ae6a27798b2573223de
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/IR/Verifier.cpp
    M llvm/test/Assembler/auto_upgrade_intrinsics.ll
    M llvm/test/CodeGen/RISCV/prefetch.ll
    M mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir

  Log Message:
  [IR] Update llvm.prefetch to match docs

The current llvm.prefetch intrinsic docs state "The rw, locality and
cache type arguments must be constant integers."

This change:
- Makes arg 3 (cache type) an ImmArg
- Improves the verifier error messages to reference the incorrect
- Fixes two tests which contradict the docs.

This is needed as the lowering to GlobalISel is different for ImmArgs
compared to other constants. The non-ImmArgs create a G_CONSTANT MIR
instruction, the for ImmArgs the constant is put directly on the
intrinsic's MIR instruction as an immediate.

Differential Revision: https://reviews.llvm.org/D132042

  Commit: 270c179afd0ecf4de5f9b00af027e2033bbcf998
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64InstrGISel.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-prefetch.ll

  Log Message:
  [AArch64][GISel] Lower llvm.prefetch

This change adds support for lowering llvm.prefetch directly using
GlobalISel. Currently, llvm.prefetch falls back to SelectionDAG.

This Change:
- Adds an AArch64-specific G_PREFETCH generic instruction, to be used
  where AArch64ISD::PREFETCH is used in SelectionDAG.
- Adds the GINodeEquiv so patterns are translated over to GlobalISel
- Corrects the AArch64Prefetch patterns to use a target immediate, which
  is needed to get the patterns to translate across correctly.
- Translates the SelectionDAG legalisation of the prefetch intrinsic
  into the corresponding GlobalISel legalisation.

Differential Revision: https://reviews.llvm.org/D132043

Compare: https://github.com/llvm/llvm-project/compare/8b50ffe9fdc3...270c179afd0e

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