[all-commits] [llvm/llvm-project] 1c8d7e: [AMDGPU] Implement pipeline solver for non-trivial...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c8d7ea973290aac4d14f5464f944c4918191cb5
      https://github.com/llvm/llvm-project/commit/1c8d7ea973290aac4d14f5464f944c4918191cb5
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2022-08-17 (Wed, 17 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
    A llvm/test/CodeGen/AMDGPU/igrouplp-dag-mutation.ll
    M llvm/test/CodeGen/AMDGPU/igrouplp-dag-mutation.mir
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    A llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir
    M llvm/test/CodeGen/AMDGPU/sched-group-barrier-pre-RA.mir

  Log Message:
  -----------
  [AMDGPU] Implement pipeline solver for non-trivial pipelines

Requested SchedGroup pipelines may be non-trivial to satisify. A minimimal example is if the requested pipeline is {2 VMEM, 2 VALU, 2 VMEM} and the original order of SUnits is {VMEM, VALU, VMEM, VALU, VMEM}. Because of existing dependencies, the choice of which SchedGroup the middle VMEM goes into impacts how closely we are able to match the requested pipeline. It seems minimizing the degree of misfit (as measured by the number of edges we can't add) w.r.t the choice we make when mapping an instruction -> SchedGroup is an NP problem. This patch implements the PipelineSolver class which produces a solution for the defined problem for the sched_group_barrier mutation. The solver has both an exponential time exact algorithm and a greedy algorithm. The patch includes some controls which allows the user to select the greedy/exact algorithm.

Differential Revision: https://reviews.llvm.org/D130797