[all-commits] [llvm/llvm-project] 232953: [AArch64] Add pattern for SQDML*Lv1i32_indexed

[OverMighty via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 232953f9962d901b6da16cf8c93ed7e2279d4804
      https://github.com/llvm/llvm-project/commit/232953f9962d901b6da16cf8c93ed7e2279d4804
  Author: OverMighty <its.overmighty at gmail.com>
  Date:   2022-08-17 (Wed, 17 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/test/CodeGen/AArch64/arm64-vmul.ll

  Log Message:
  -----------
  [AArch64] Add pattern for SQDML*Lv1i32_indexed

There was no pattern to fold into these instructions. This patch adds
the pattern obtained from the following ACLE intrinsics so that they
generate sqdmlal/sqdmlsl instructions instead of separate sqdmull and
sqadd/sqsub instructions:
 - vqdmlalh_s16, vqdmlslh_s16
 - vqdmlalh_lane_s16, vqdmlalh_laneq_s16, vqdmlslh_lane_s16,
   vqdmlslh_laneq_s16 (when the lane index is 0)

It also modifies the result of the existing pattern for the latter, when
the lane index is not 0, to use the v1i32_indexed instructions instead
of the v4i16_indexed ones.

Fixes #49997.

Differential Revision: https://reviews.llvm.org/D131700