[all-commits] [llvm/llvm-project] 0af465: [RISCV] Add scheduling class for vector pseudo seg...

[Monk Chiang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0af4651c0fc7d8887c7086381f6f514132899b20
      https://github.com/llvm/llvm-project/commit/0af4651c0fc7d8887c7086381f6f514132899b20
  Author: Monk Chiang <monk.chiang at sifive.com>
  Date:   2022-08-16 (Tue, 16 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Add scheduling class for vector pseudo segment instructions.

Add scheduling resource for vector segment load/store instructions in D128886.
I miss to add scheduling resource for pseudo segment instructions.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D130222