[all-commits] [llvm/llvm-project] cfd2c5: Untangle the mess which is MachineBasicBlock::hasA...

[Eli Friedman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cfd2c5ce580fce744f6fd6ba34e869cab05e94c3
      https://github.com/llvm/llvm-project/commit/cfd2c5ce580fce744f6fd6ba34e869cab05e94c3
  Author: Eli Friedman <efriedma at quicinc.com>
  Date:   2022-08-16 (Tue, 16 Aug 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.cpp
    M llvm/lib/CodeGen/MIRParser/MILexer.h
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    M llvm/lib/Target/VE/VEISelLowering.cpp
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86IndirectThunks.cpp
    M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
    R llvm/test/CodeGen/AArch64/branch-target-enforcement.mir
    M llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
    M llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
    M llvm/test/CodeGen/ARM/ifcvt-size.mir
    M llvm/test/CodeGen/Hexagon/bank-conflict.mir
    M llvm/test/CodeGen/Hexagon/hwloop-redef-imm.mir
    M llvm/test/CodeGen/Hexagon/loop_correctness.ll
    M llvm/test/CodeGen/Hexagon/pipeliner/swp-phi-start.mir
    M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
    M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
    M llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
    M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
    M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
    M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
    M llvm/test/CodeGen/X86/callbr-asm-kill.mir
    M llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
    M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
    M llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir
    M llvm/test/DebugInfo/MIR/X86/ldv_unreachable_blocks.mir
    M llvm/test/DebugInfo/MIR/X86/ldv_unreachable_blocks2.mir
    M llvm/test/tools/llvm-reduce/mir/preserve-block-info.mir
    M llvm/tools/llvm-reduce/ReducerWorkItem.cpp

  Log Message:
  -----------
  Untangle the mess which is MachineBasicBlock::hasAddressTaken().

There are two different senses in which a block can be "address-taken".
There can be a BlockAddress involved, which means we need to map the
IR-level value to some specific block of machine code.  Or there can be
constructs inside a function which involve using the address of a basic
block to implement certain kinds of control flow.

Mixing these together causes a problem: if target-specific passes are
marking random blocks "address-taken", if we have a BlockAddress, we
can't actually tell which MachineBasicBlock corresponds to the
BlockAddress.

So split this into two separate bits: one for BlockAddress, and one for
the machine-specific bits.

Discovered while trying to sort out related stuff on D102817.

Differential Revision: https://reviews.llvm.org/D124697