[all-commits] [llvm/llvm-project] 7a73ab: [RISCV] Enable isTruncateFree in SDAG for i64->i32...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7a73ab5818a1e9d849efdbccd5e3181356612d05
      https://github.com/llvm/llvm-project/commit/7a73ab5818a1e9d849efdbccd5e3181356612d05
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-15 (Mon, 15 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    A llvm/test/CodeGen/RISCV/trunc-free.ll

  Log Message:
  -----------
  [RISCV] Enable isTruncateFree in SDAG for i64->i32 on rv64.

We have a good selection of W instructions, so promoting a truncated
value back to i64 is often free.

This appears to be a net code size reduction on SPECINT2006.

This has been split from D130397 as one of the patches needed to
complete that.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D131819