[all-commits] [llvm/llvm-project] de4871: [AVR] Support unaligned store

[Ayke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de48717fcf1c340517beb8beb488c627e6e3d034
      https://github.com/llvm/llvm-project/commit/de48717fcf1c340517beb8beb488c627e6e3d034
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2022-08-15 (Mon, 15 Aug 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    R llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
    A llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll

  Log Message:
  -----------
  [AVR] Support unaligned store

This patch really just extends D39946 towards stores as well as loads.
While the patch is in SelectionDAGBuilder, it only applies to AVR (the
only target that supports unaligned atomic operations).

Differential Revision: https://reviews.llvm.org/D128483


  Commit: 43a8dbc5be8ae9d31fb86f333794e51280ea3992
      https://github.com/llvm/llvm-project/commit/43a8dbc5be8ae9d31fb86f333794e51280ea3992
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2022-08-15 (Mon, 15 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    R llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir

  Log Message:
  -----------
  [AVR] Use @earlyclobber instead of register scavenging

The code to support the case when the register allocator has assigned
the same register to the src and the dst register operand isn't actually
needed:

  * LDWRdPtr and LDDWRdPtrQ have an @earlyclobber on the output
    register, so the register allocator will make sure to allocate a
    different register for the output register.
  * LDDWRdYQ does not have an @earlyclobber, but the pointer register is
    the fixed Y register which is reserved. The register allocator won't
    use reserved registers for the output value.

This removes a special case in the code that makes the pseudo
instruction expansion pass more complicated than it needs to be.

Differential Revision: https://reviews.llvm.org/D131844


  Commit: a560e57a7e32d7da3fd897b3d09ee541911eed65
      https://github.com/llvm/llvm-project/commit/a560e57a7e32d7da3fd897b3d09ee541911eed65
  Author: Ayke van Laethem <aykevanlaethem at gmail.com>
  Date:   2022-08-15 (Mon, 15 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
    M llvm/lib/Target/AVR/AVRFrameLowering.cpp
    M llvm/lib/Target/AVR/AVRISelLowering.cpp
    M llvm/lib/Target/AVR/AVRInstrInfo.td
    M llvm/test/CodeGen/AVR/interrupts.ll
    M llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
    A llvm/test/CodeGen/AVR/pseudo/ROLBrd.mir
    A llvm/test/CodeGen/AVR/zeroreg.ll

  Log Message:
  -----------
  [AVR] Only push and clear R1 in interrupts when necessary

R1 is a reserved register, but LLVM gives the APIs to know when it is
used or not. So this patch uses these APIs to only save/clear/restore R1
in interrupts when necessary.

The main issue here was getting inline assembly to work. One could argue
that this is the job of Clang, but for consistency I've made sure that
R1 is always usable in inline assembly even if that means clearing it
when it might not be needed.

Information on inline assembly in AVR can be found here:

https://www.nongnu.org/avr-libc/user-manual/inline_asm.html#asm_code

Essentially, this seems to suggest that r1 can be freely used in avr-gcc
inline assembly, even without specifying it as an input operand.

Differential Revision: https://reviews.llvm.org/D117426


Compare: https://github.com/llvm/llvm-project/compare/5371ab445618...a560e57a7e32