[all-commits] [llvm/llvm-project] 6e85db: [DAGCombine] Combine signext_inreg of extract-extend

[Peter Waller via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e85db729300b1625e129c9d2661a91397705ce6
      https://github.com/llvm/llvm-project/commit/6e85db729300b1625e129c9d2661a91397705ce6
  Author: Peter Waller <peter.waller at arm.com>
  Date:   2022-08-15 (Mon, 15 Aug 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
    M llvm/test/CodeGen/AArch64/vector-fcvt.ll

  Log Message:
  -----------
  [DAGCombine] Combine signext_inreg of extract-extend

The outer signext_inreg is redundant in the following:

  Fold (signext_inreg (extract_subvector (zext|anyext|sext iN_value to _) _) from iN)
       -> (extract_subvector (signext iN_value to iM))

Tests are precommitted and clone those by analogy from the AND case in
the same file. Add a negative test to check extension width is handled
correctly.

This patch supersedes D130700.

Differential Revision: https://reviews.llvm.org/D131503