[all-commits] [llvm/llvm-project] 2c7980: [RISCV] Add more ineg+setcc isel patterns to avoid...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2c79801a0e572e1f25a249596d963ad178cfcda5
      https://github.com/llvm/llvm-project/commit/2c79801a0e572e1f25a249596d963ad178cfcda5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-11 (Thu, 11 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Add more ineg+setcc isel patterns to avoid creating neg+xori+slti(u).

Including patterns to select addiw if only the lower 32 bits are used.

I'm not excited about adding this many patterns. I'm looking at whether
we can create the xori during lowering and move the ineg patterns to
DAGCombiner.