[all-commits] [llvm/llvm-project] a9e9dd: [AArch64] Add bf16 select handling

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9e9dd9a3a44d88cda85d0b26778c80faf5355d2
      https://github.com/llvm/llvm-project/commit/a9e9dd9a3a44d88cda85d0b26778c80faf5355d2
  Author: David Green <david.green at arm.com>
  Date:   2022-08-11 (Thu, 11 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-fmax.ll
    A llvm/test/CodeGen/AArch64/bf16-select.ll
    M llvm/test/CodeGen/AArch64/f16-instructions.ll

  Log Message:
  -----------
  [AArch64] Add bf16 select handling

A bfloat select operation will currently crash, but is allowed from C.
This adds handling for the operation, turning it into a FCSELHrrr if
fullfp16 is present, or converting it to a FCSELSrrr if not. The
FCSELSrrr is created via using INSERT_SUBREG/EXTRACT_SUBREG to convert
the bf16 to a f32 and using the f32 pattern for FCSELSrrr. (I originally
attempted to do this via a tablegen pattern, but it appears that the
nzcv glue is places onto the wrong node, causing it to be forgotten and
incorrect scheduling to be emitted).

The FCSELSrrr can also be used for fp16 selects when +fullfp16 is not
present, which helps avoid an unnecessary promotion to f32.

Differential Revision: https://reviews.llvm.org/D131253