[all-commits] [llvm/llvm-project] 7bece0: [LLDB][RISCV] Add riscv register definition and re...

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7bece0f03bf6cbf7f98812b7cff0e789709c9982
      https://github.com/llvm/llvm-project/commit/7bece0f03bf6cbf7f98812b7cff0e789709c9982
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2022-08-11 (Thu, 11 Aug 2022)

  Changed paths:
    M lldb/source/Host/common/HostInfoBase.cpp
    M lldb/source/Plugins/Process/Linux/CMakeLists.txt
    A lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
    A lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
    M lldb/source/Plugins/Process/Utility/CMakeLists.txt
    A lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
    A lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
    A lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
    A lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
    A lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
    M lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h

  Log Message:
  -----------
  [LLDB][RISCV] Add riscv register definition and read/write

This patch is based on the minimal extract of D128250.

What is implemented:
- Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
- Refactor some duplicate code, and delete unused register definitions.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D130342