[all-commits] [llvm/llvm-project] 3f8ae7: [AMDGPU] SIFixSGPRCopies refactoring

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f8ae7efa866e581a16e9ccc8e29744722f13fff
      https://github.com/llvm/llvm-project/commit/3f8ae7efa866e581a16e9ccc8e29744722f13fff
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2022-08-10 (Wed, 10 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

  Log Message:
  -----------
  [AMDGPU] SIFixSGPRCopies refactoring

This change finalizes the series of patches aiming to replace old
strategy of VGPR to SGPR copies loweriong.  Following the
https://reviews.llvm.org/D128252 and https://reviews.llvm.org/D130367 code
parts that are no longer used were removed.  Pass main loop is no longer used
for the MIR changes but collect information for further analysis.  Actual MIR
lowering happens further according the analysys result in the set of separate
functions. Another important change concerns the order of lowering: VGPR to
SGPR copies lowering is done first to have priority on the rest of the MIR
changes.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D131246