[all-commits] [llvm/llvm-project] aaf6c7: [globalisel] Select register bank for DBG_VALUE

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aaf6c7b05c9d155c8d34ec06a2f76ebdef8d21b9
      https://github.com/llvm/llvm-project/commit/aaf6c7b05c9d155c8d34ec06a2f76ebdef8d21b9
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2022-08-09 (Tue, 09 Aug 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
    M llvm/lib/CodeGen/RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/lib/Target/X86/X86RegisterBankInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-dbg-value.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-hint.mir
    M llvm/test/DebugInfo/AArch64/debug-reg-bank.ll
    M llvm/test/DebugInfo/X86/debug-reg-bank.ll

  Log Message:
  -----------
  [globalisel] Select register bank for DBG_VALUE

The register operand of DBG_VALUE is not selected to a proper register
bank in both AArch64 and X86. This would cause getRegClass crash after
global ISel. After discussion, we think the MIR should assume all
vritual register should be set proper register class after global ISel,
so this patch is to fix the gap of DBG_VALUE for AArch64 and X86.

Differential Revision: https://reviews.llvm.org/D129037