[all-commits] [llvm/llvm-project] 1206f7: [AArch64] Fold Mul(And(Srl(X, 15), 0x10001), 0xfff...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1206f72e31f6d67069f1c90c4871b229923008a4
      https://github.com/llvm/llvm-project/commit/1206f72e31f6d67069f1c90c4871b229923008a4
  Author: David Green <david.green at arm.com>
  Date:   2022-08-02 (Tue, 02 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/insert-extend.ll
    M llvm/test/CodeGen/AArch64/mulcmle.ll
    M llvm/test/CodeGen/AArch64/reduce-shuffle.ll

  Log Message:
  -----------
  [AArch64] Fold Mul(And(Srl(X, 15), 0x10001), 0xffff) to CMLTz

This folds a v4i32 Mul(And(Srl(X, 15), 0x10001), 0xffff) into a v8i16
CMLTz instruction. The Srl and And extract the top bit (whether the
input is negative) and the Mul sets all values in the i16 half to all
1/0 depending on if that top bit was set. This is equivalent to a v8i16
CMLTz instruction. The same applies to other sizes with equivalent
constants.

Differential Revision: https://reviews.llvm.org/D130874