[all-commits] [llvm/llvm-project] 768e59: [LLDB][RISCV] Add riscv register enums

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 768e59d959c7e23e98cda1b08c5b6b68dbc1d2a7
      https://github.com/llvm/llvm-project/commit/768e59d959c7e23e98cda1b08c5b6b68dbc1d2a7
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2022-08-02 (Tue, 02 Aug 2022)

  Changed paths:
    A lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h

  Log Message:
  -----------
  [LLDB][RISCV] Add riscv register enums

According to [RISC-V ISA Spec](https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf) and [riscv-v-spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#3-vector-extension-programmers-model)

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D130899