[all-commits] [llvm/llvm-project] e07a81: [RISCV] Move Pre-RA pseudo expansion from addMachi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e07a8155f5168fdaff9346152d7805a47cb49405
      https://github.com/llvm/llvm-project/commit/e07a8155f5168fdaff9346152d7805a47cb49405
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-01 (Mon, 01 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll

  Log Message:
  -----------
  [RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc.

addMachineSSAOptimization is skipped for -O0, but this pass is
required for -O0.