[all-commits] [llvm/llvm-project] 0bc177: [RISCV] Extend the Merge Base Offset pass to handl...

[Luís Marques via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bc177b6f54bbd0b03c4f2378039b676463ff7b9
      https://github.com/llvm/llvm-project/commit/0bc177b6f54bbd0b03c4f2378039b676463ff7b9
  Author: Luís Marques <luismarques at lowrisc.org>
  Date:   2022-08-01 (Mon, 01 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/test/CodeGen/RISCV/codemodel-lowering.ll
    M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
    M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

  Log Message:
  -----------
  [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

Builds upon D123264, adding support for merging the low part of the LLA
address into the load/store instruction offsets.

Differential Revision: https://reviews.llvm.org/D123265