[all-commits] [llvm/llvm-project] f47355: [LLDB][RISCV] Add DWARF Registers

[Emmmer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f473558647705a042de9d5ec96c23a21f2005bb1
      https://github.com/llvm/llvm-project/commit/f473558647705a042de9d5ec96c23a21f2005bb1
  Author: Emmmer <yjhdandan at 163.com>
  Date:   2022-07-30 (Sat, 30 Jul 2022)

  Changed paths:
    A lldb/source/Utility/RISCV_DWARF_Registers.h

  Log Message:
  -----------
  [LLDB][RISCV] Add DWARF Registers

According to [RISC-V DWARF Specification](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc) add RISCV DWARF Registers.

Don't worry about the difference between riscv32 and riscv64, they just have different bytes of registers.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D130686