[all-commits] [llvm/llvm-project] f47355: [LLDB][RISCV] Add DWARF Registers
Emmmer via All-commits
all-commits at lists.llvm.org
Fri Jul 29 21:06:14 PDT 2022
Author: Emmmer <yjhdandan at 163.com>
Date: 2022-07-30 (Sat, 30 Jul 2022)
[LLDB][RISCV] Add DWARF Registers
According to [RISC-V DWARF Specification](https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc) add RISCV DWARF Registers.
Don't worry about the difference between riscv32 and riscv64, they just have different bytes of registers.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D130686
More information about the All-commits