[all-commits] [llvm/llvm-project] f93182: [clang-format] Handle Verilog numbers and operators

[eywdck2l via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f93182a887889828fc6c963174afd7d7b3625e5a
      https://github.com/llvm/llvm-project/commit/f93182a887889828fc6c963174afd7d7b3625e5a
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/FormatTokenLexer.cpp
    M clang/lib/Format/FormatTokenLexer.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog numbers and operators

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D126845


  Commit: 67480b360ca0dcc33fe3126d0602b3d358dfbc6f
      https://github.com/llvm/llvm-project/commit/67480b360ca0dcc33fe3126d0602b3d358dfbc6f
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog blocks

Now stuff inside begin-end blocks get indented.

Some tests are moved into FormatTestVerilog.Block from
FormatTestVerilog.If because they have nothing to do with if statements.

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D128711


  Commit: 6db0c18b1af653f33dd4629d6155f6cf334a975e
      https://github.com/llvm/llvm-project/commit/6db0c18b1af653f33dd4629d6155f6cf334a975e
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/TokenAnnotator.h
    M clang/lib/Format/UnwrappedLineFormatter.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog modules

Now things inside hierarchies like modules and interfaces are
indented.  When the module header spans multiple lines, all except the
first line are indented as continuations.  We added the property
`IsContinuation` to mark lines that should be indented this way.

In order that the colons inside square brackets don't get labeled as
`TT_ObjCMethodExpr`, we added a check to only use this type when the
language is not Verilog.

Differential Revision: https://reviews.llvm.org/D128712


  Commit: b67ee18e85f30334792e33a71c883fcfdcb83436
      https://github.com/llvm/llvm-project/commit/b67ee18e85f30334792e33a71c883fcfdcb83436
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog user-defined primitives

Differential Revision: https://reviews.llvm.org/D128713


  Commit: c88719483c69f7f34be4487f6623b06c37475e5a
      https://github.com/llvm/llvm-project/commit/c88719483c69f7f34be4487f6623b06c37475e5a
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/ContinuationIndenter.cpp
    M clang/lib/Format/Format.cpp
    M clang/lib/Format/FormatToken.h
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/lib/Format/UnwrappedLineParser.h
    M clang/unittests/Format/FormatTestVerilog.cpp
    M clang/unittests/Format/TokenAnnotatorTest.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog case statements

These statements are like switch statements in C, but without the 'case'
keyword in labels.

How labels are parsed.  In UnwrappedLineParser, the program tries to
parse a statement every time it sees a colon.  In TokenAnnotator, a
colon that isn't part of an expression is annotated as a label.

The token type `TT_GotoLabelColon` is added.  We did not include Verilog
in the name because we thought we would eventually have to fix the
problem that case labels in C can't contain ternary conditional
expressions and we would use that token type.

The style is like below.  Labels are on separate lines and indented by
default.  The linked style guide also has examples where labels and the
corresponding statements are on the same lines.  They are not supported
for now.

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md

```
case (state_q)
  StIdle:
    state_d = StA;
  StA: begin
    state_d = StB;
  end
endcase
```

Differential Revision: https://reviews.llvm.org/D128714


  Commit: 60e12068ffeb96aa4e56c8dcff3442e516b27ab6
      https://github.com/llvm/llvm-project/commit/60e12068ffeb96aa4e56c8dcff3442e516b27ab6
  Author: sstwcw <f0gukp2nk at protonmail.com>
  Date:   2022-07-29 (Fri, 29 Jul 2022)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/lib/Format/UnwrappedLineParser.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Handle Verilog attributes

Reviewed By: HazardyKnusperkeks, owenpan

Differential Revision: https://reviews.llvm.org/D128709


Compare: https://github.com/llvm/llvm-project/compare/241f0e8b76d5...60e12068ffeb