[all-commits] [llvm/llvm-project] 82c1b1: [LV] Don't predicate uniform mem op stores unnecce...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82c1b136dbe10760241fabf13c635f78a509e744
      https://github.com/llvm/llvm-project/commit/82c1b136dbe10760241fabf13c635f78a509e744
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-07-28 (Thu, 28 Jul 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/pr46525-expander-insertpoint.ll

  Log Message:
  -----------
  [LV] Don't predicate uniform mem op stores unneccessarily

We already had the reasoning about uniform mem op loads; if the address is accessed at least once, we know the instruction doesn't need predicated to ensure fault safety. For stores, we do need to ensure that the values visible in memory are the same with and without predication. The easiest sub-case to check for is that all the values being stored are the same. Since we know that at least one lane is active, this tells us that the value must be visible.

Warning on confusing terminology: "uniform" vs "uniform mem op" mean two different things here, and this patch is specific to the later. It would *not* be legal to make this same change for merely "uniform" operations.

Differential Revision: https://reviews.llvm.org/D130637