[all-commits] [llvm/llvm-project] 8d87f7: [RISCV] Pre-commit tests for D130610. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d87f71e548e8241927db90d09379b893cbd5944
      https://github.com/llvm/llvm-project/commit/8d87f71e548e8241927db90d09379b893cbd5944
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-27 (Wed, 27 Jul 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/narrow-shl-cst.ll

  Log Message:
  -----------
  [RISCV] Pre-commit tests for D130610. NFC


  Commit: a304d70ee9b8611b60eb1951cbf62cd447520a36
      https://github.com/llvm/llvm-project/commit/a304d70ee9b8611b60eb1951cbf62cd447520a36
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-27 (Wed, 27 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/test/CodeGen/RISCV/narrow-shl-cst.ll

  Log Message:
  -----------
  [RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.

InstCombine and DAGCombine prefer to keep shl before binops.

This patch teaches isel to convert to (shl (and/or/xor X, C1 >> C2), C2)
if (C1 >> C2) is a simm12. The idea was taken from X86's isel code.

There's a special case implemented for a sext_inreg between the
shift and the binop.

Differential Revision: https://reviews.llvm.org/D130610


Compare: https://github.com/llvm/llvm-project/compare/1d1d8d6025a2...a304d70ee9b8