[all-commits] [llvm/llvm-project] 343488: [AArch64] Explicitly use v1i64 type for llvm.aarch...

[Mingming Liu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 34348814e127163d00825fe98bb1c04cebc459a1
      https://github.com/llvm/llvm-project/commit/34348814e127163d00825fe98bb1c04cebc459a1
  Author: Mingming Liu <mingmingl at google.com>
  Date:   2022-07-27 (Wed, 27 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
    M llvm/test/CodeGen/AArch64/arm64-vmul.ll
    A llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll

  Log Message:
  -----------
  [AArch64] Explicitly use v1i64 type for llvm.aarch64.neon.pmull64

Without this, the intrinsic will be expanded to an integer; thereby an
explicit copy (from GPR to SIMD register) will be codegen'd. This matches the
general convention of using "v1" types to represent scalar integer operations in
vector registers.

The similar approach is observed in D56616, and the pattern likely applies on
other intrinsic that accepts integer scalars (e.g.,
int_aarch64_neon_sqdmulls_scalar)

Differential Revision: https://reviews.llvm.org/D130548