[all-commits] [llvm/llvm-project] 1ea7b9: [DAG] matchRotateSub - set demanded bits to the sh...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ea7b9c6ee6420dd6e87489534f44b92e1b6f220
      https://github.com/llvm/llvm-project/commit/1ea7b9c6ee6420dd6e87489534f44b92e1b6f220
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-07-26 (Tue, 26 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAG] matchRotateSub - set demanded bits to the shift amount type size, not the shift result size.

This should fix a report on D130251 of an assert due to a bitwidth mismatch in APInt::isSubSetOf