[all-commits] [llvm/llvm-project] 1a7078: [DAGCombine] Mask doesn't have to be (EltSize - 1)...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a7078d1064b4bac6a6b3ac66682b8a76852bf94
      https://github.com/llvm/llvm-project/commit/1a7078d1064b4bac6a6b3ac66682b8a76852bf94
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2022-07-26 (Tue, 26 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  [DAGCombine] Mask doesn't have to be (EltSize - 1) exactly when combining rotation

I think what we need is the least Log2(EltSize) significant bits are known to be ones.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D130251