[all-commits] [llvm/llvm-project] 290c4b: [LLDB][ARM] Generalise adding register state in em...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 290c4bc7be45a29d98ea2e8460ef50f4924a1c4b
      https://github.com/llvm/llvm-project/commit/290c4bc7be45a29d98ea2e8460ef50f4924a1c4b
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2022-07-26 (Tue, 26 Jul 2022)

  Changed paths:
    M lldb/source/Plugins/Instruction/ARM/EmulationStateARM.cpp
    M lldb/source/Plugins/Instruction/ARM/EmulationStateARM.h

  Log Message:
  -----------
  [LLDB][ARM] Generalise adding register state in emulation tests and add D registers

Since some s and d registers overlap we will error if we find both.
This prevents you overwriting one with the other in a test case.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D130462