[all-commits] [llvm/llvm-project] 1db6d6: [RISCV] Teach RISCVCodeGenPrepare to optimize (zex...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1db6d6dcd888540574e5ada6dadc09029e5e79ec
      https://github.com/llvm/llvm-project/commit/1db6d6dcd888540574e5ada6dadc09029e5e79ec
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-25 (Mon, 25 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
    M llvm/test/CodeGen/RISCV/iabs.ll

  Log Message:
  -----------
  [RISCV] Teach RISCVCodeGenPrepare to optimize (zext (abs(i32 X, i1 1))).

(abs(i32 X, i1 1) always produces a positive result. The 'i1 1'
means INT_MIN input produces poison. If the result is sign extended,
InstCombine will convert it to zext. This does not produce ideal
code for RISCV.

This patch reverses the zext back to sext which can be folded
into a subw or negw. Ideally we'd do this in SelectionDAG, but
we lose the INT_MIN poison flag when llvm.abs becomes ISD::ABS.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D130412