[all-commits] [llvm/llvm-project] add17f: [RISCV] Combine (select_cc (srl (and X, 1<<C), C), ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: add17fc8e4ceb78fb7eafac49d519001c168bd7a
      https://github.com/llvm/llvm-project/commit/add17fc8e4ceb78fb7eafac49d519001c168bd7a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-20 (Wed, 20 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/bittest.ll

  Log Message:
  -----------
  [RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)

(srl (and X, 1<<C), C) is the form we receive for testing bit C.
An earlier combine removed the setcc so it wasn't there to match
when we created the SELECT_CC. This doesn't happen for BR_CC because
generic DAG combine rebuilds the setcc if it is used by BRCOND.

We can shift X left by XLen-1-C to put the bit to be tested in the
MSB, and use a signed compare with 0 to test the MSB.