[all-commits] [llvm/llvm-project] 523a52: [LV] Fix miscompile due to srem/sdiv speculation s...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 523a526a024fb2835c998d1c054698cc16da87f4
      https://github.com/llvm/llvm-project/commit/523a526a024fb2835c998d1c054698cc16da87f4
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-07-20 (Wed, 20 Jul 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Transforms/LoopVectorize/RISCV/scalable-divrem.ll

  Log Message:
  -----------
  [LV] Fix miscompile due to srem/sdiv speculation safety condition

An srem or sdiv has two cases which can cause undefined behavior, not just one. The existing code did not account for this, and as a result, we miscompiled when we encountered e.g. a srem i64 %v, -1 in a conditional block.

Instead of hand rolling the logic, just use the utility function which exists exactly for this purpose.

Differential Revision: https://reviews.llvm.org/D130106