[all-commits] [llvm/llvm-project] 4c82f5: [llvm][SVE] Remove redundant and when comparing ag...

[David Truby via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c82f56d8fb9266f46d11c293aa10f53153ecf69
      https://github.com/llvm/llvm-project/commit/4c82f56d8fb9266f46d11c293aa10f53153ecf69
  Author: David Truby <david.truby at arm.com>
  Date:   2022-07-19 (Tue, 19 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/AArch64/sve-extload-icmp.ll

  Log Message:
  -----------
  [llvm][SVE] Remove redundant and when comparing against extending load

When determining if an `and` should be merged into an extending load
the constant argument to the `and` is currently not checked if the
argument requires truncation. This prevents the combine happening when
the vector width is half the normal available vector width for SVE VLA
vectors.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D129281