[all-commits] [llvm/llvm-project] 0f6b04: [DAG] SimplifyDemandedBits - relax "xor (X >> Shif...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f6b0461b01dfb1be4b359a1b9b328e1085f81d8
      https://github.com/llvm/llvm-project/commit/0f6b0461b01dfb1be4b359a1b9b328e1085f81d8
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-07-19 (Tue, 19 Jul 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/test/CodeGen/Mips/bittest.ll
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/X86/speculative-load-hardening.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" to match only demanded bits

The "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" fold is currently limited to the XOR mask being a shifted all-bits mask, but we can relax this to only need to match under the demanded bits.

This helps expose more bit extraction/clearing patterns and fixes the PowerPC testCompares*.ll regressions from D127115

Alive2: https://alive2.llvm.org/ce/z/fl7T7K

Differential Revision: https://reviews.llvm.org/D129933