[all-commits] [llvm/llvm-project] 464b3a: [RISCV] Pre-commit tests for D129980. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 464b3a9d8a1a86b53278c2ecc59db78dcaf0593f
      https://github.com/llvm/llvm-project/commit/464b3a9d8a1a86b53278c2ecc59db78dcaf0593f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/i64-icmp.ll

  Log Message:
  -----------
  [RISCV] Pre-commit tests for D129980. NFC

Differential Revision: https://reviews.llvm.org/D129981


  Commit: 0b0275289961dd49315bcb3b8dfcae5687f23eaa
      https://github.com/llvm/llvm-project/commit/0b0275289961dd49315bcb3b8dfcae5687f23eaa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/i64-icmp.ll

  Log Message:
  -----------
  [RISCV] Optimize (seteq (i64 (and X, 0xffffffff)), C1)

(and X, 0xffffffff) requires 2 shifts in the base ISA. Since we
know the result is being used by a compare, we can use a sext_inreg
instead of an AND if we also modify C1 to have 33 sign bits instead
of 32 leading zeros. This can also improve the generated code for
materializing C1.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D129980


Compare: https://github.com/llvm/llvm-project/compare/42fdb487d76a...0b0275289961