[all-commits] [llvm/llvm-project] 7c0b9b: [RISCV] Add isel patterns for ineg+setge/le/uge/ule.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c0b9b379b0e36ec1ed76ab5a4386e80dafd53fc
      https://github.com/llvm/llvm-project/commit/7c0b9b379b0e36ec1ed76ab5a4386e80dafd53fc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-18 (Mon, 18 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/select-const.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for ineg+setge/le/uge/ule.

setge/le/uge/ule selected by themselves require an xori with 1.
If we're negating the setcc, we can fold the xori with the neg
to create an addi with -1.

This works because xori X, 1 is equivalent to 1 - X if X is either
0 or 1. So we're doing -(1 - X) which is X-1 or X+-1.

This improves the code for selecting between 0 and -1 based on a
condition for some conditions.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D129957